UVC/UVM VIP

The Verification IP (VIP) for the Tensilica Processor Interface (PIF)  provides a quick and efficient way to verify PIF based SoC designs by implementing advanced techniques for more productive verification.PIF eVC is the complete solution for the verification of PIFbased systems. It has a complete built-in set of predefined coverage items and protocol checkers that are fully compliant with PIF protocol. Most of possible PIF scenarios are defined trought predefined sequences. PIF eVC can be used verification environments both at module, subsystem and system level.

The purpose of HSV 900 is to provide reusable verification solution for serial flash memories (such as Spansion S25FL). The verification environment is developed in SystemVerilog using Universal Verification Methodology (UVM) version 1.0 Current version of HSV 900 is intended for verification of Spansion S25FL-S serial flash memories (its behavioral VITAL or other behavioral models). Verification environment can be easily modified for verification of other serial flash VITAL models by setting the model parameters and by using type and instance overrides provided by UVM. This enables the testing of not only Spansion serial flash memory models, but also the models from other vendors, such as Atmel, Sanyo, Micronix, SST, Numonyx and Winbond.