Junior Verification Engineer

Job Description

Why we need you:

To help us make a SoC (System on a chip) chip that changes the world.

Who can apply:

Candidates with formal education, Sc. or B. Sc. degree in Electronics, Informatics, Computer Science, Automatic, Telecommunications or Electrical engineering.
Your Responsibilities:
Involvement in all stages of complex SoC verification including specification, test-bench design, verification plan, development, verification execution and verification sign off.
Proactive collaboration with team members in different locations
Review of the verification environment architecture and implementation specifications

What you’ll bring:
Good knowledge of object-oriented programming
Knowledge of C/C++ and computer architecture

Bonus points if you are:

Familiar with scripting tools and languages (e.g. bash, csh, awk, Perl).
Familiar with software/hardware development tools (e.g. make and versioning tools (e.g. CVS/SVN).
Familiar with complex flows for System-on-Chip projects.

Why to choose to work for HDL Design House:

For all junior engineers there will be 4-6 months technical training. It will be organized in HDL DH premises, executed by senior engineer with teaching experience from the Faculty of Electrical Engineering. The training will be organized based on Cadence (Incisive/Xcelium, Genus, Innovus, Tempus) and Mentor (QuestaSim) EDA tools. During the training period, the junior engineers will not have other assignments and they will have fully paid salary.
Permanent employment
Private health insurance
Opportunity to be part of many sports activities: football, basketball, volleyball ..
Team building gatherings, traveling and parties.
English classes
Company sponsored trainings, domestic and international conferences, workshops and education
Working in young and enthusiastic team