HDL Design House invites you to join the free January 29th, 2019 webinar on optimizing SoC development challenges and achieving reduced time-to-market and built-in security.
Belgrade, Serbia – January 15th, 2019 – HDL Design House, provider of digital, analog, and back-end design and verification services and products in numerous areas of SoC, will host a webinar with Arm on SoC design and verification best practices for accelerated time-to-market on January, 29th, 2019. The webinar will be presented by Mike Eftimakis, senior IoT product manager, Arm and Vojislav Krvavac, digital design engineer, HDL Design House.
With increased complexity of designing secure SoC, along with growing challenges in integration and verification stages, managing SoC design efficiently has become a crucial component for successful tape-out. The latest trends and developments in the semiconductor industry demand advanced and integrated solutions to meet aggressive schedules without compromising quality.
The webinar will address the above requirements, providing the attendees answers on how to reduce design and integration effort, lower design risk and accelerate time-to-market. The webinar presenters will also illustrate real life example of overcoming challenges and achieving customer requirements quickly and efficiently. Finally, the reasons why security should be a cornerstone of SoC design and how to reduce time-to-security will be given.
This online event is intended for engineering directors, design and verification managers and engineers needing to optimize SoC development activities for schedule, budgets and technical excellence.
The webinar is taking place on Tuesday, January 29th, 2019, at 9am and 5pm GMT and is free to attend. Joining instructions are available on the webinar registration page.