Belgrade, Serbia – May 8th, 2014 – HDL Design House invites students and graduates of electrical engineering to attend the lecture “Introduction to ASIC & FPGA Verification” at the Faculty of Electrical Engineering, Belgrade University, room 61, on May 14th from 2pm-4pm.

The first part of the lecture will present the latest trends in ASIC and FPGA verification, and introduce random verification as the best verification method. Attendees will learn about a typical structure of a verification environment and its benefits, as well as all phases of a verification project. The lecture aims to provide introduction to functional verification for students who are interested to know more about the current verification methodologies.

About the speaker: Olivera Stojanovic graduated from the Faculty of Electrical Engineering, Belgrade University, Department of Computer Engineering and Information Technologies. She has been working for HDL Design House as Verification Team Leader for ten years on various verification projects related to the avionics industry, mobile platforms,etc. Customers on whose projects she worked include Honeywell, LSI, Texas Instruments, Broadcom, AMD, and Cadence.

To register for the lecture, please fill in the registration form on the following link:

http://goo.gl/z9dXzH

For more information, please contact:

Milena Jovanovic
Marketing Manager
HDL Design House
phone: +381 (0)11 7859 557
email: m-jovanovic@hdl-dh.com

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