HDL Design House New Verification Seminar in Austin: Maximizing Verification Efficiency

Belgrade, Serbia – August 28th, 2014

HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, will organize a full day seminar in Austin, Texas, to be held at Hyatt Place Austin Downtown on September 19th, 2014. The seminar will include presentations from HDL Design House, Freescale and Cadence verification experts, addressing topics related to maximization of verification efficiency.

When/Where

Friday, September 19th, 2014
9.00 am – 4.00 pm, lunch included
Hyatt Place Austin Downtown
211 E 3rd St,
Austin, TX 78701,
United States
http://austindowntown.place.hyatt.com/en/hotel/home.html

To register for the seminar please visit:
http://www.hdl-dh.com/seminar4.html

Participation is free of charge. Lunch and refreshments will be served.
The seminar is relevant for design & verification managers and engineers and semiconductor professionals.

Agenda and Speakers’ Topics:

9.00 – 9.30 Coffee & Registration

9.30 – 10.00 HDL Design House – Verification Expertise and Portfolio Predrag Markovic, HDL DH CEO
HDL Design House delivers leading-edge digital and analog design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops digital and analog IP cores and offers back-end services.

10.00 – 12.00 Verification Process Enhancement
Olivera Stojanovic, Senior Staff Verification Engineer, HDL DH
Marko Olujic, Senior Verification Engineer, HDL DH
This presentation shows how to maximize verification effectiveness in conjunction with the UVM. Besides standard UVM approach of reusing UVCs through different projects, the presentation introduces different flavors of reuse. The presentation demonstrates ways how to speed up verification environment implementation, debug process and decrease simulation time.

12.00 – 12.15 Coffee Break

12.15 – 13.15 Cadence VIP Catalog
Tom Hackett, Product Marketing Director at Cadence Design Systems
This presentation will provide an overview of the Cadence Verification IP (VIP) Catalog. The VIP Catalog provides advanced simulation models for over 40 standard interfaces and 6000 memory components. By supporting multiple logic simulators and verification languages including SystemVerilog UVM, the VIP Catalog makes it easy to boost the efficiency of your verification environment.

13.15 – 14.30 Lunch

14.30 – 15.00 UVM SoC Hardware/Software Coordination
Alan Carlin, Freescale
Verification of contemporary SoCs typically includes an embedded software component, in addition to the HLVL testbench infrastructure. This presentation discusses some techniques for coordinating the execution of software driven stimulus within a UVM based testbench for a multi-core SoC. Utilizing a generalized memory-based communication mechanism, the embedded software can raise and drop objections, control UVM VIP, and launch sequences.

15.00 – 15.30 Real Valued Modeling for SoC Simulations
Chris Tsiavos, Freescale
Mixed-signal applications are among the fastest growing market segments in the semiconductor industry. As the number of analog components in a modern day SoC increases, there is a need for Verilog behavioral models of mixed-signal circuits that simulate accurately and efficiently. The IEEE 1800TM-2012 SV-RNM extensions to the SystemVerilog language allow verification of analog block operations using discretely simulated real values. This presentation describes modeling analog blocks with real number modeling (RNM) and how they are used for the verification of SoC interconnect.

15.30 – 16.00 Wrap-up & Networking

Contact information:

Milena Jovanovic
Marketing Manager
HDL Design House
Phone: +381 (0)11 7859 557
Email: m-jovanovic@hdl-dh.com