Digital IP Cores

The JESD204B RX Physical Coding Sublayer IP Core (HIP610) enables the reception of data via a configurable number of lanes from a Deserializer interface, while guaranteeing data alignment and frame synchronization. The HIP610 IP Core performs 8b/10b decoding, frame recovery, lane alignment, descrambling, and data demapping functions. In addition, it contains a set of test features, necessary to validate the data integrity on the serial interface. The HIP610 IP Core supports configurable number of DAC ports, each one having a width of up to 32 bits. The HIP610 IP Core offers the possibility to modify the behavior of the design based on the application requirements. This is done through the use of the design parameters, as well as via the Configuration Interface by programming the configuration registers.

Runs at speeds of up to 4 Gbps per lane Supports between 1 – 32 lanes Uses data scrambling to reduce EMI signature Targeted for low-power, high-speed digital video data trans- mission Performs data alignment and synchronization Includes link monitoring functions Supports a variety of video resolutions (HD, Full HD, Cinema Full HD, 4K x 2K) Allows for the transmission of 3D video Features color depths of 18,24, 30, & 36 bits per pixel Supports video refresh rates of 60, 120, 240 & 480 Hz

Runs at speeds of up to 4Gbps per lane
Supports between 1 – 32 lanes
Uses data scrambling to reduce EMI signature
Targeted for low-power, high-speed digital video data
transmission
Performs data alignment and synchronizations
Includes link monitoring functions
Allows for the transmission of 3D video
Features color depths of 18,24, 30 & 36 bits per pixel
Supports video refresh rates of 60, 120, 240 & 480 Hz
Supports a variety of video resolutions (HD, Full HD, Cinema Full HD, 4k x 2k)

The JESD204B TX Physical Coding Sublayer IP Core (HIP600) enables the transmission of data via a configurable number of lanes from a Serializer interface. The HIP600 IP Core performs data mapping, scrambling, alignment character insertion and 8B/10B encoding functions. In addition, it contains a set of test features, necessary to validate the data integrity on the serial interface. The HIP600 IP Core offers the possibility to modify the behavior of the design based on the application requirements. This is done through the use of the design parameters, as well as via the Configuration Interface by programming the configuration registers.

The Physical Coding Sublayer (PCS) IP Core enables transmission and reception of data via 8-Lanes SerDes interface. It is able to multiplex a synchronous digital stream of data over 8 Lanes, while guaranteeing data alignment and super-frame synchronization. The PCS is responsible for idle sequence generator, lane striping and encoding for transmission and decoding, lane aligment and restriping on reception. The PCS uses an 8B/10B encoding for transmission over the link.

CSI-2 (Camera Serial Interface) Transmitter IP core is highly configurable, synthesizable digital IP core which receives pixels from camera sensor, performs packing in form of long packets, and Short packets, and sends them via PPI interface to the Host processor. Designed for use in portable electronic devices such as media players, mobile phones, and personal assistant devices, the CSI-2 Transmitter IP core is fully compliant to MIPI Alliance’s CSI standard, as well as to AMBA’s AHB specification.

The HIP 3510 is a highly configurable, synthesizable digital IP core, used to exchange pixels and command data between a video source (host processor) and a display peripheral. Designed for use in portable electronic devices such as media players, mobile phones, and personal assistant devices, HIP3510 is fully compliant to MIPI Alliance’s DSI, DPI-2, and DCS standards, as well as to AMBA’s AHB specification.

DSI (Display Serial Interface) defines protocol between host processor and a peripheral such as Display device, based on MIPI Alliance specifications for mobile devices interfaces, which operates with pixels and command sets specified in the DPI-2, DBI-2 and DCS standards. Its purpose is to send pixels and commands to the peripheral such as Display and receives back pixel or status information from the peripheral.

HDL DH UniPro IP core (HIP3600 and from this point onwards use HIP3600) complies with the UniPro specification version 1.4. HIP3600 implements the Physical-Adapter Layer (L.15), Data Link Layer (L2), Network Layer (L3) and Transport Layer (L4) as well as support the M-PHY Layer of the standard. HIP3600 exhibits a complete set of component with bus-master and slave interfaces using AMBA AHB and AXI Version 2.0.

I2S is an audio transmission standard, used to connect system elements such as Analog to Digital and Digital to Analog converters, speakers or audio subsystems. HIP 3700 is silicon proven I2S Controller IP Core compliant to the Philips* Inter-IC Sound specification. IP Core provides up to 8 audio channels and a 32-bit parallel processor bus as the application interface. Each channel can be programmed as an I2S master or an I2S slave.

Serial RapidIO is a data communication standard provisioned for the interconnection of devices on the same circuit board or between circuit boards across a backplane. It has been developed as a more cost-effective, standards, switched based replacement for expensive proprietary buses in high-performance embedded systems, such as networking and communications equipment and enterprise storage.

SPI flash memory controller allows flexible, fast and high performance implementation of an AHB subsystem having SPI flash memories and offloading AHB master from direct control of SPI flash memories and executes SPI data operations. It supports up to 16 flash memory devices of any memory size organized in up to 4 memory clusters. AHB master configures SPI controller, provides necessary data (in the case of memory write operation) or read data (in the case of memory read operation) and starts SPI controller. SPI controller can decode and execute SPI flash memory instructions controlling directly SPI flash memories and offload AHB master from this task.

The HCR_AES crypto core family is high-performance family of cores that allow the implementation of the NIST FIPS PUB 197 algorithm in hardware. These cores can be integrated into SoC designs.