Verilog/VHDL/SystemVerilog RTL Code Development

VHDL/Verilog code development, functional and timing simulations. HDL code and testbench development. Functional testing of design, testbench development and HDL code testing. The ASIC specification and RTL microarchitecture can be developed according to the customer's requirements, also. Development of architectural and/or microarchitectural ASIC specification, implementation and verification related documents necessary for the ASIC design and implementation

Development of synthesis scripts using different synthesis tools. The target technology could be "silicon" or FPGA. We can also optimize your HDL code for the specific implementation technology.

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