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October 03, 2007
HDL DH verification IP presentation at the AETC in Paris, France

On October 25th 2007 HDL Design House will participate in the 2007 ARM European Technical Conference (AETC) in Paris. This event's objective is to give key decision makers and designers from across Europe the opportunity to learn first hand about advantages of designing with ARM (www.arm.com) and ARM Partner solutions. Other exhibitors at this event will be: Cadence, Synopsis, Texas Instruments, Synplicity, etc. .

In its presentation, HDL Design House will demonstrate the use of its verification IP (VIP) products. Apart from other VIP from HDL DH portfolio, the following products related to ARM technology will be presented in detail:

AMBA AHB SystemVerilog Testsuite (HVC 700)
AMBA APB SystemVerilog Testsuite (HVC 710)

HVC 700 is a SystemVerilog Testsuite incorporating assertion based AMBA AHB protocol Monitor/Checker. It is fully compliant with AMBA specification, and other verification environment components: stimulus generator, AHB Masters/Slaves, AHB Arbiter/Multiplexer, Coverage collector and Error analysis block. 26 AHB protocol checks are implemented in HVC 700 AHB Monitor component as SVA assertions. In addition, HVC 700 is fully compliant with SystemVerilog specification Mentor Graphics Advanced Verification Methodology (AVM, Cookbook-1.2). HVC 710 is a SystemVerilog Testsuite that incorporates assertion based APB protocol Monitor/Checker, fully compliant with AMBA3 specification, and other verification environment components: stimulus generator, APB bridge, APB slave, coverage collector and error analysis block. 20 APB protocol checks are implemented in HVC 710 APB Monitor component as SVA assertions. Further, HVC 710 is fully compliant with SystemVerilog specification and Mentor Graphics Advanced Verification Methodology (AVM, Cookbook-1.2).

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