IP Products
UniPro Soft IP Core
HIP 3200 soft IP core complies with the UniPro specification
version 1.0. It implements the PHY Adapter, Data Link,Network, and Transport Layers of the standard. A system-onchip (SoC) bus master controller, interrupt controller, clockreset-power management, and a SoC bus slave interface are also included to ease integration with different types of
embedded systems.
The Soft IP Core can be configured to work on one and up to four data lanes for transmit and for receive. Each data lane can have a maximum raw data rate of up to 800 Mbps.
In the version 1.0 of UniPro specification, only the short form of Network and Transport layer headers are supported but the soft IP core is forward compatible with future revisions of the standard. Up to 128 device IDs can be addressed in a network. Detection of unsupported features on the L3 level are also provided. Hardware based support for the Transport layer are implemented in the UniPro Soft IP. Up to 2048 independent CPorts that are equivalent to logical connections can be managed. Autonomous segmentation and reassembly of Application layer messages are performed in the hardware level.
Product Code Name
HIP 3200 |
Datasheet
 |
Return to Top of Page
....................................................................................
BCH Codec IP Core
BCH codes can be used to create concatenated code with increased performance.
BCH codec is an IP core containing both encoder and decoder. BCH codec IP Core (HIP 2900) can
be used for a variety of applications, including disk players, audio techniques, digital video broadcast
products, wireless communication products, broadband modems, satellite communications
products, space projects and storage devices. The two main applications for BCH codec IP Core
(HIP 2900) are data transmission and data storage:
Data transmission dedicated BCH architectures overcome channel noise and
transmission data corruption.
Data storage dedicated BCH architectures overcome physical media imperfection.
Product Code Name
HIP 2900 |
Datasheet
|
Return to Top of Page
....................................................................................
Golay Encoder/Decoder IP Core
Hip golay encoder/decoder IP cores delivers technology independent,structural Verilog HDL design that can be applied to a set of industry standards handling error correction schemes. The encoder core will process the incoming vector to generate parity data For the incoming sequence evaluated as corrupted, the error distribution over the symbol block needs to be derived. Determined error locations enable the error correction to be performed.Data corruption may exceed the decoding error correction capabilities, decoding process will failand signal the failure.
Product Code Name
HIP 4000 |
Datasheet
|
Return to Top of Page
....................................................................................
Reed Solomon IP Core
Solomon codes, a class of error correction codes, are block-oriented coding schemes
used in communication systems for FEC (Forward Error Correction). Information coding prior to transmission is performed against limited
transmit power/bandwidth. ReedSolomon decoding architectures contribute to systems that are sensitive to transmission errors, with no data
acknowledge or data retransmit. They are well suited for correcting errors that occur in bursts. Combined with a Viterbi coding scheme,
ReedSolomon codes can be used to create concatenated code with increased performance.
Product Code Name
HIP 2500 |
Datasheet
|
Return to Top of Page
....................................................................................
APB SPI Lite IP Core
The APB SPI Lite IP core is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to
the Advanced Peripheral Bus (APB) on one side, and to a Motorola SPI 4-wire interface on the other. It is a slave interface for synchronous
serial communication with peripheral devices that support Motorola SPI synchronous serial interface. With an AMBA APB interface on one
side, the module allows low-bandwidth peripheral devices with Motorola SPI synchronous serial interfaces to be connected to an Advanced
High-Performance Bus (AHB). Such interfaces do not require a high-performance pipeline bus interface.
Product Code Name
HIP 3000 |
Datasheet
|
Return to Top of Page
....................................................................................
PSPP1284 IEEE 1284 Parallel Port Controller
The PSPP1284 core implements the IEEE 1284 interface. Software-programmable for the operation as a host or peripheral device, the core
supports Compatible, Nibble, Byte, EPP, and ECP mode of operations and includes a configurable depth FIFO tightly coupled with the DMA
engine for efficient data transfer in ECP mode. Full-speed data transfer can be performed by initializing the core in ECP operation mode
with DMA transfer enabled, and waiting for an interrupt at completion. The core provides a solution for parallel ports that requires
minimal software assistance.
Product Code Name
IEEE 1284 |
Datasheet
|
Return to Top of Page
....................................................................................
HCR_DES_TDES Crypto Core Family
The HCR_DES_TDES crypto core family is group of high-performance crypto cores that implement the NIST FIPS
PUB 46-3 algorithm in hardware. This family of IP crypto cores can be used to enable integration in today’s SoC designs
Product Code Name
HIP 1100 |
Datasheet
|
Return to Top of Page
....................................................................................
HCR_AES Crypto Core Family
The HCR_AES crypto core family is high-performance family of cores that allow the implementation of the NIST
FIPS PUB 197 algorithm in hardware. These cores can be integrated into SoC designs.
Product Code Name
HIP 1000 |
Datasheet
|
Return to Top of Page |
