Design and Verification Services
HDL Design House is a leading regional service provider for SoC systems design and verification. Using its comprehensive design and verification methodology, the company has designed and verified some of the industry’s most complex SoC, ASIC’s and FPGA’s. For complex system solutions, verification must be an integral part of the design process from the start, along with synthesis, system software and lab debug strategies. HDL Design House has developed a verification strategy and guidelines that will allow rapid closure of the verification effort.
HDL Design House also offers development of Universal Verification Components (uVCs), a new line of reusable verification IP (VIP) that integrates compliance management and mixed-language flexibility with advanced simulation-based testbench technology. UVCs are part of the next generation verification methodology that spans the entire verification process, maximize quality, predictability and efficiency.
HDL Design House offers following verification services:
- Verification plan development
- Verification environment development
- Transactor and Bus Models development
- Assertions development and integration
- Transactional / Functional / Cycle accurate models in C, C++, SystemC, e, SystemVerilog
- Properties and assertion formal proof development
- Development of testcases/vectors covering system functionalities in C, C++, HDL testbench, SystemVerilog and Specman
- Code coverage ananalysis, testbench development, design and code reviews, script development
HDL Design House offers following design services:
- Microarchitecture definition
- RTL code development and RTL code review (VHDL/Verilog/SystemVerilog)
- Synthesis, timing, power optimization
- Assertions development and integration
- Design verification
- ATPG/DFT
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